The present invention relates in general to the testing of integrated circuits and, more particularly, to latching the output state of a comparator circuit to allow static leakage current testing in the gate array.
High-speed data transmission systems often use low-level signals across the transmission medium in order to achieve high data switching speeds. Low-level signals switch faster because there is less charging and discharging of nodal and cross capacitances. In digital data systems, the digital signals are often converted to low amplitude analog signals for transmission. The analog signal signals are converted back to digital signals at the receiving end of the transmission system typically with analog comparators.
The receiving end of the transmission system often utilizes large scale integrated semiconductor gate arrays, typically 100,000 gates and more, for the comparator function and other digital processing. The large scale gate arrays generally use sub-micron CMOS transistors to achieve high speeds and high packing densities. As such, the small feature size geometries equate to transistor gate oxides that are typically less than 100 angstroms in thickness. Since there are a large number of gates in the array, the thin gate oxide represents an opportunity for oxide defect failures. Static leakage current tests, where no switching occurs during the test, have been implemented at the circuit level to verify the oxide integrity.
In arrays that utilize solely digital logic, the task of testing is straightforward. A logic test vector is applied to the gate array to exercise each gate oxide and the logic gates are allowed to reach steady-state with the given test vector. The resultant static leakage current is then measured. Additional test vectors are used to completely test the gate array. The static leakage current should be in nanoamp range if the gate oxides are good. Leakage currents in the microamp range indicate a possible defective oxide.
Testing becomes more difficult when analog comparators are added to the front-end of the gate arrays for converting the low-level analog signals back to digital logic levels. Typical data transmission systems encompass 2-bit or 64-bit parallel input signals, thus requiring 32 or 64 analog comparators respectively. Since the comparators consume static currents in the milliamp range, it is difficult to measure nanoamp to microamp leakage currents of other logic gates in the array. The comparator static current swamps any measurement of the logic gates static leakage current. Attempts to remove power from the comparators in the prior art to eliminate their effect on the logic gate static leakage current testing have proven ineffective because of the unpredictability of the output states of the comparators when power is removed. Some logic gates are not tested because the associated comparator output state is undefined. Therefore, total quality compliance cannot be assured simply by removing power from the comparators.
Hence, a need exists to power-down the analog comparator front-end while maintaining its output logic state to provide reliable testing of static leakage currents of other logic gates.